For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. It has become increasingly significant to rely heavily on innovative fabrication techniques to meet the exceedingly tight tolerance requirements imposed by scaling.
Non-volatile embedded memory with RRAM devices, e.g., on-chip embedded memory with non-volatility can enable energy and computational efficiency. However, the technical challenges of creating an appropriate stack for fabrication of RRAM devices that exhibit high device endurance, high retention and operability at low voltages and currents presents formidable roadblocks to commercialization of this technology today. Specifically, the objective of memory technology to control tail bit data in a large array of memory bits necessitates tighter control of the variations in metal oxide break down and switching events in individual bits. Furthermore, in filamentary RRAM systems, the latter is dictated by fine tuning oxygen vacancy concentration which is widely understood to drive filament formation and dissolution in metal oxide films. As such, significant improvements are still needed in the area of metal oxide stack engineering which rely on material advancements, deposition techniques or a combination of both. This area of process development is an integral part of the non-volatile memory roadmap.